Provides negative output pulse width equal to positive input pulse multiplied by 1 + R4/R3, which is 11 for values shown. Output pulses are TTL-or DTL-compatible. Minimum output pulse width is 70 ns, and maximum is 1/11 of pulse repetition rate. Circuit consists of switched current source, switched current sink, integrating capacitor, and comparator. Q1 and Q2 act as switches for current sources Q3 and Q4, while C1 and C2 reduce turn-on and turnoff times of switches. CR1 and CR2 provide temperature compensation for Q3 and Q4. AND gate compensates for propagation delay in NOR gate, to ensure that current sink is switched on by trailing edge of input pulse. Add inverter if output must be same polarity as input.-F. Tarico, Linear Circuit Multiplies Pulse Width, EDN|EEE Magazine, Dec. 1, 1971, p 45-46.
Required Field 
